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rev. 1.0 november 2013 www.aosmd.com page 1 of 14 AOZ3024PI ezbuck? 3 a synchronous buck regul a tor ge neral desc ription th e aoz3 024 pi is a high e f ficien cy , ea sy to u se, 3 a synchr ono us buck r e g u lato r . the aoz30 24pi wo rks fr om 4 . 5 v to 1 8 v inp u t vo lt ag e ra ng e, and pr ovide s u p to 3 a o f continu o u s ou tp ut cu rr ent with a n ou tp ut vo lt age ad ju st a b le d o w n to 0. 8 v . th e aoz3 024 pi come s in a n expo se d p a d so- 8 p a ckage a n d is ra te d over a -40 c to +85 c oper ating a m bie n t tem per atur e ra ng e. features ? 4.5 v to 18 v ope ra tin g inp u t volt a g e r a n g e ? synchr ono us bu ck: 70 m ? internal high-side switc h an d 40 m ? internal low-side s witc h (at 12 v) ? up to 95 % ef ficie n cy ? exte rn al so f t st ar t ? ou tp ut vo lt ag e adju s t a ble to 0.8 v ? 3 a co ntinu ous ou tp ut cur r ent ? 50 0 khz pwm o per ation ? cy cle-by-c ycle current limi t ? pr e- bia s s t ar t- up ? sh or t- circ uit pr o tec tio n ? th er mal shut d o wn ? exposed p a d so- 8 p a ckag e app l ications ? poin t- of- l oad dc/dc co nver te rs ? lcd tv ? set- to p boxe s ? dvd an d blu- ra y pla y ers/re co rd er s ? ca ble m o de m s typical application figure 1 . 3.3 v , 3 a syn c hr on ou s buc k reg u lator , fs = 5 00 khz lx vin vin vout fb pgnd en comp agnd c2, c3 22f r1 r2 c c r c c1 10f l1 4.7h AOZ3024PI pgood r3 5v http://
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 2 of 14 ordering information aos green prod uct s use redu ced level s o f hal ogen s, and a r e a l so rohs compl i ant. please visit w w w . a o smd . co m/medi a/aosgre enpol icy . p d f for addi ti onal i n formati on. pin configuration pin description part number ambien t temperature range package env i r onmen t a l AOZ3024PI -40 c to +85 c epad so-8 green product 1 2 3 4 pgnd vin a gnd fb exposed pad so-8 (t op view) pad (lx) lx pgood en comp 8 7 6 5 pin number pin nam e pin f unct i on 1 p gnd p ow er g r ound . pgnd n eed s to be ele c trica lly conne cte d to agnd. 2 v in sup p ly volt age i nput. w hen vin rises above the uvlo th re shold a nd en is l ogic hi gh, the device st art s up. 3 a gnd a na log g r o und . agnd i s the reference p o int fo r con t rol l er secti on. agnd ne eds to b e e l ectrically con nected to pgnd. 4 f b f eed back in put. th e f b pin is used to set t he o u tput volt ag e via a resistive vo lt age divid e r b e tween the ou tp ut an d agnd. 5 c omp e xternal loop compe n sation p i n. c onne ct a rc network betwee n comp and agnd to comp ensate the control loo p . 6 e n e na ble p i n. pu ll en to lo gic high to en able the de vice. pu ll en to lo gic low to disab l e th e d e vice. if o n /of f con t rol i n not n eed ed, co nnect en to vin a nd do no t lea ve it op en. 7 p good pow e r goo d output. pgood is a n open -drain o u tp ut tha t ind i cates th e st atus of ou tp ut volt a ge. 8 l x (sense) no c onne ct pin. pin 8 is n o t i n te rnall y con nected. conn ect this pin e xte rn ally to lx a nd us e it fo r be tt er th e rma l p e rf or ma nce . expo sed p a d l x s wi tchi ng nod e. l x is t he drai n o f the intern al pfet . l x is used a s the thermal p a d o f the po w e r st ag e .
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 3 of 14 block diagram abso lute maximum ratings exceedi ng the absolu te maximu m ratin g s ma y da ma ge the devi c e . no te: 1. devices are inher ently esd s ensitive, handlin g precautions are requ ire d . human bo dy mod e l r a ting : 1.5 k ? in series with 100 pf . recommended operating conditions th e device i s no t gua ranteed to op erate beyon d the maxi mu m reco mmen ded opera t in g cond itions. 500khz oscillator agnd pgnd vin en fb comp pgood lx otp internal +5v ilimit pwm control logic 5v ldo regulator uvlo & por softstart reference & bias 0.8v q1 q2 pwm comp level shifter + fet driver isen eamp + ? + ? frequency foldback comparator + ? + ? + 0.2v over-voltage protection comparator + ? 0.96v + ? 0.72v parameter ra ti ng supp ly v o l t ag e (v in )2 0 v lx to ag nd -0 .7 v to v in + 0 .3 v lx to agnd (20 ns) - 5 v to 2 2 v en to ag nd -0 .3 v to v in + 0 .3 v f b , pg oo d, co mp t o agnd -0.3 v to 6.0 v pgnd t o agnd -0 .3 v to + 0 . 3 v junction t e mp erature (t j ) +15 0 c s t or ag e t e mp e r at ur e (t s ) - 65 c to + 1 50 c esd rating (1) 2.0 kv parameter rating supp ly v o lt a ge (v in ) 4 .5 v to 18 v outp ut v o l t ag e rang e 0 .8 v to 0.85 * v in amb i e n t t e mp er at ure ( t a ) - 40 c to + 85 c pa cka ge th er ma l resist ance e x po se d pa d so-8 ( ? ja ) 50 c/w
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 4 of 14 electrical characteristics t a = 25 c, v in = v en = 12 v , v out = 3. 3 v u n l e ss ot he rw i se sp ec if ie d . (2 ) no te: 2. s pecification in bold indica te an ambient temper ature range of -40 c to +85 c . these specificati ons are guarante ed by design. symbol par a meter conditions min. typ. max. uni t s v in supp ly v o l t a g e 4.5 1 8 v v uv l o input unde r-v o l t a ge lockou t th reshol d v in risin g v in fa llin g 4. 1 3. 7 v i in supp ly c u rrent (qui escent) i ou t = 0, vfb = 1.2 v , v en > 2 v 1 .6 2.5 m a i off shut do wn suppl y cu rre n t v en = 0 v 11 0 a v fb fe edb ack v o l t ag e t a = 25 c 0 . 7 8 8 0 .8 0.812 v loa d regu lation 0. 5 % lin e regu lation 1% i fb fe edb ack v o l t ag e in put c u rrent 20 0 n a v en en in put t h resh old o f f t h resho l d on t h reshold 2 0.6 v v hy s en in put h y steresi s 2 0 0 m v en leaka ge curren t 1 a ss t ime 34.56 ms modulator f o fre quen cy 400 5 0 0 6 0 0 khz d max maximum duty cycle 8 5 % t min controllable m i nimum on t i me 150 n s curren t sense t r an scondu ct an ce 8 a / v error ampl ifier transconductance 200 a / v protection i li m c u rre nt l i m i t 3 .5 4. 5 a v ov p o v er- v o l t a ge pr ot ect i on of f th re sh ol d on t h reshold 96 0 80 0 mv ove r -t e m p e rature shut dow n limit t j ri si n g t j fal ling 15 0 10 0 c po wer goo d v ol p g pg lo w v o l t ag e i ol = 1ma 0 .25 v pg le akage 1 a v pgl pg t h reshol d v o lt a ge (risin g) 8 8 91 93 % / v pg t h reshol d hyste r e s is 3 % t pg pg delay time 128 s ou tput st age hig h-side switch on -resist ance v in = 12 v v in = 5 v 70 11 0 m ? low-si de switch on -r esist a nce v in = 12 v v in = 5 v 40 50 m ?
rev. 1.0 november 2013 www.aosmd.com page 5 of 14 AOZ3024PI t y pical performance ch aracteristics circuit of figure 1. t a = 25 c, v in = v en = 12 v, v out = 3. 3 v u n le ss ot he rw ise sp ec ified . light load operation 2s/div start up to full load 5ms/div full load operation 2s/div short ci rcuit protectio n 20ms/div short ci rcuit recove ry 20ms/div vin ripple 0.5v/div vo ripple 50mv/div vlx 10v/div il 2a/div vin 5v/div vo 2v/div vo 2v/div vlx 10v/div il 2a/div vo 2v/div vlx 10v/div il 2a/div 50% to 100% load transient 100s/div vo ripple 0.2v/div io 2a/div vin ripple 0.2v/div vo ripple 50mv/div vlx 10v/div il 2a/div
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 6 of 14 efficiency det a iled description th e aoz3 024 pi is a cu rr en t- mod e ste p down r egu lator with a n integr ated h i gh- side pmos switch a nd a low-side nmos switch. the aoz30 24pi ope ra te s fro m a 4.5 v to 1 8 v in put vo lt ag e ra nge a n d sup p lie s up to 3 a of load cur r e n t. fea t ure s includ e ena ble contr o l, p o wer - on r e set, in put und er vo lt age lo cko u t, ou tp ut over volt a g e p r otection , exter n a l sof t - s t a rt and the r m a l sh ut down. th e aoz3 024 pi is availab l e in an e x posed p a d so-8 p a ckage . enable and sof t s t art th e aoz3 024 pi ha s a n inter nal sof t st a r t fe atur e to limit in -r ush cu rr en t an d en su re the o u tpu t volt a ge r a mp s u p smoo thly to r egu lation volt a g e . th e so f t st ar t p r oce s s b egin s whe n th e inp u t volt a g e r i ses to 4.1 v an d vo lt ag e on t h e en pin is hi gh . in t h e s o f t st art proc es s, the o u tput volt ag e is typica lly r a mp ed to r e g u lation vo lt ag e in 4. 5ms. the 4.5ms s o f t st art time is s e t internally . th e en p i n o f th e aoz30 24pi is a c tive h i gh. co nne ct the en pin to vin if the enable function is not used. pulling en to ground will disable th e AOZ3024PI. do not leav e en o p e n . t he volt a ge on th e en pin m u st be abo ve 2 v to e nab le the aoz3 024 pi. whe n the en pin volt ag e falls be lo w 0 .6 v , the a oz 3 02 4pi is dis a b l ed . power good the power good outpu t is an op en d r ai n n- chan nel mosfet wh ich su pplie s a n active- h ig h po we r go od st ag e. a pu ll-u p re sistor sho u ld con nect th is pin to a dc p o we r tr ail w i th m a xim u m vo lt ag e of 6 v . t h e a oz 3 02 4p i also mo nitor s the f b volt a ge. when the fb volt a g e is lowe r th an 9 0 % o f the n o r m al volt ag e, th e n- chan ne l mosfet tu rn s o n an d the po we r go od p i n is pulle d lo w , this indicates the po wer is abn or mal. s t e a dy -s t a t e op era t ion und e r h eavy lo ad stead y- st ate cond itio ns, the co nver te r op er ates in fixed fr equ en cy an d co ntinu ous- c o ndu ctio n m o d e (c cm ). th e aoz30 24pi in te gr ates an in te rn al p- mosfet as the hig h - s id e switch . in ductor cur r e n t is sensed b y a m pli f ying the volt a ge d r op across th e dr ain to sour ce of the high side p o wer m o sfet . ou tp ut vo lt ag e is divid ed do wn by the e x ter n a l volt a g e d i vid e r a t the f b pi n. th e dif f er ence of th e fb pin volt a ge a nd r e fer ence volt a ge is a m plifie d by the inter n a l tr anscon duct a n ce er ror amp lifie r . the er ro r volt a ge, wh ich sh ows o n th e comp pin , is comp ar ed aga inst th e cur r e n t sig n a l , which is the su m of in du cto r cu rr en t s i gn al an d ra mp co m p e n sa t io n s i gn al, a t the pwm co mp ar ator in pu t. if th e curr en t sign al is less than th e er ro r volt a ge, the in te rn al hig h - s id e switch is on. efficiency (v in = 12v, l = 4.7h) vs. load current 100 95 90 85 80 75 70 65 60 55 50 0 0.5 1.0 1.5 2 .0 2.5 3 .0 l o ad c u r r en t ( a ) efficiency (%) 5v output 3.3v output 1.8v output 1.2v output
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 7 of 14 th e ind u cto r cur r en t flows fr om the in put th ro ugh th e inductor to the output. when th e cu rr en t si gnal exceeds the er ro r volt ag e, the h i gh- side switch is of f. the in ductor cur r e n t is free whee ling thr o u gh the in te rn al low-side n-mo sfet sw itch to output. th e inter nal ad ap tive fet d r iver g u a r an te es no tur n on o v e r la p of b o th the h i gh- side an d the low- sid e switch. comp a r ed with r egu lator s u s in g fr ee wh ee ling schottky dio d e s , t h e ao z 3 0 2 4 p i us es a fr ee wh ee lin g nm osf e t to r e a lize sy nch r on ou s re ct ification. this greatly im pr ov es th e co nv er te r e f f i cien cy a n d r e d u c e s p o we r los s in the low-s i de s witch. th e aoz3 024 pi use s a p-ch ann el mosf et a s the high-side sw itch. this s a v e s the boot s t rap cap a citor normally seen in a circuit using an nmos sw itch. outp ut v o lt a g e progr amming output vo lt ag e ca n be set by fe edin g ba ck th e ou tp ut to the fb pin using a r e sisto r divide r ne twor k a s sho w n in fig u r e 1. t he r e sisto r divide r ne twor k in clude s r 1 an d r 2 . usually , a de sig n is st ar ted by picking a fixed r 2 valu e and ca lcu l ating the r e q u ir ed r 1 with the eq ua tio n below: som e st a n d a rd va lue of r 1 an d r 2 for the most common o u tput vo lt ag es a r e listed in t a b l e 1. t a bl e 1. th e co mbin ation o f r 1 a nd r 2 sho u ld be la rg e eno ugh to a v o i d dr awing e x cessive cu rr ent from the outpu t, which will c a use pow e r loss. protection features th e aoz3 024 pi ha s mu lti p le pr otection fea t u r e s to pr even t system cir c u i t da mag e un der abn or mal conditions. ov er curre nt pro t ec tion ( o cp) th e se nsed in ductor cu rr ent si gna l is also used fo r over cu rr en t pr ot ec tio n . sinc e th e aoz 3 02 4 p i e m plo ys pe a k cur r e n t m ode con t rol, the comp pin vo lt age is pr op or tio nal to the pe ak indu c t or c u r r e n t . t h e com p pin volt age is limited to be between 0.4 v and 2 . 5 v internally . th e pea k in ductor cur r ent is au toma tically limited cy cle-by-c ycle. whe n th e ou tp ut is sh or te d to gr oun d un der fa ult con d itions, th e indu cto r cu rr en t slowly d e cays d u r i ng a switchin g cycle be ca use the ou tput vo lt ag e is 0 v . t o pr even t cat a stro ph ic failur e , aoz3 024 pi de te ct s the du ra tio n when the over -cur re nt con d ition o ccu rs. if the ove r - cur r e n t con d ition occur s fo r a ce rt a i n p e r i od of time , ao z3024pi completely turn s o f f mom ent a r ily , th en rest art s . if the fault is still pres ent, then the dev i ce will turn of f again. the c o nverter will initiate a sof t st art once the o v e r - c u r r e n t cond ition disa ppe ar s. power-o n reset (p or) a p o wer - on r e set circuit m onitor s the inpu t vo lt ag e. when the in put vo lt ag e exce ed s 4. 1 v , th e conver ter st ar t s op er ation . when inpu t volt a ge falls belo w 3.7 v , the conv erter will be shut down. the rmal prot ect ion an in te rn al tem p er a t ur e se ns or m o n i to rs th e ju nct i on temp er atur e. t he sen s o r shut s down the in tern al contr o l circuit an d high sid e pmos if the ju nctio n temp er atur e exceeds 150 oc. the regulato r w ill rest art automatically u n d e r th e co n t ro l of th e so f t - st a rt cir cu i t wh en th e ju nc tio n temp er atur e decr ease s to 100 oc. v o (v) r 1 (k ? ) r 2 (k ? ) 0.8 1 .0 op en 1.2 4 .99 1 0 1.5 1 0 1 1.5 1.8 1 2 . 7 1 0.2 2.5 2 1 . 5 1 0 3.3 3 1 . 1 1 0 5.0 5 2 . 3 10 v o 0. 8 1 r 1 r 2 -- -- -- - + ?? ?? ?? ? =
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 8 of 14 application information th e ba sic aoz3 024 pi ap plication cir c u i t is sh ow in fig u r e 1. co mpo nen t sele ction i s expla i ne d belo w . input ca p acit o r th e inpu t ca p a cito r must be con nected to th e v in p i n and the pgnd pin o f aoz3 02 4pi to ma int a in stea dy in pu t volt a ge an d filte r ou t the p u lsing in put cu rr en t. the volt a ge r a ting o f inp u t ca p a citor must b e gr eate r th an ma xim u m inp u t vo lt age plus rip p le volt a ge. th e inp u t r i pp le vo lt ag e ca n be a ppr oxima t e d by e qua tio n be low: since the in pu t cur r en t is disco n tinu ous in a bu ck co nv er te r , th e c u r r e n t st re ss on t h e in pu t ca p a c i to r is a nothe r co ncer n whe n sele ctin g the cap a citor . for a buck circui t, th e rm s valu e of inpu t cap a citor cur r e n t ca n be ca lcu l at ed b y: if w e let m eq ua l the co nver sio n ra tio : th e re lation sh ip be twee n th e inp u t ca p a citor rm s cu rr en t an d vo lt ag e co nv er sio n ra tio is c a lc ula t e d an d sho w n in f i gur e 2 b e low . it ca n be see n that wh en v o is ha lf of v in , c in is under the w o rst current s t ress . the wors t current stress on c in is 0.5 x i o . fig u re 2 . i cin vs . v o lt age co nv ers i o n ratio fo r re liab l e ope ra tio n an d best per form ance , the inp u t cap a citors mus t have a cu rrent rating higher than i ci n_rms at th e wor s t ope ra tin g cond itio ns. cer a m i c cap a citor s ar e pr efer re d fo r inp u t ca p a cito rs becau se of thei r low esr an d high cu rr ent ra tin g . de pen ding on the ap plication cir c u i t s, othe r low esr t a n t alu m ca p a cito rs ma y be used. whe n se lectin g cer a m i c ca p a citor s, x5 r or x7r typ e diele c tr ic cer a mic ca p a cito rs sh ou ld be use d fo r th eir b e t t er t e m p er at ur e an d vo lt ag e ch ar ac te rist ics. note that t h e ripple curr ent rating f r om cap a citor ma nufactur e s are based o n a cer t ain op er ating life time. fu rthe r de -r ating ma y n eed to b e co nside r e d fo r lon g term reli ability . induc to r th e indu cto r is u s e d to su pply const a n t cur r e n t to o u tput whe n it is dr ive n by a switchin g vo lt ag e. for a given in put an d ou tp ut vo lt age , in duct a n c e and switch ing fre que ncy toge ther decide th e indu cto r rip p le cur r e n t, which is: th e pea k in ductor cur r ent is: high induct a nce gives low inductor ripp le cur r ent b u t r equ ire s lar g e r size in du ctor to a v o i d satur a tion. lo w r i pple cu rr ent re duces ind u ct or core losses. it also r edu ce s rms cu rr en t thr oug h ind u cto r an d switches, which re sult s in le ss cond uction loss. usuall y , pe ak to pe ak rip p le cur r e n t o n th e ind u cto r is d e sign ed to be 20 % to 40 % of outpu t cur r e n t. whe n se lecting the in ductor , con f ir m it is able to h and le the p eak cu rr en t with o u t satur a tion a t the hig h e s t op er ating tem per atur e. th e indu cto r t a kes th e hig hest cu rr ent in a bu ck circuit. th e cond uctio n loss on the indu cto r ne eds to be ch ecke d for the r m a l and e f ficien cy re qu irem ent s. sur f ace mo un t in du ctor s in d i f f er en t sh ape an d style s are ava ilable fr om coilcra f t , elyton e an d mur a t a . shie lde d ind u ctor s are sma ll an d r a d i ate less emi no ise . however , they cost more than uns h ie ld ed in du ct or s. th e ch oic e de pe nds on emi re quir e m ent, p r ice an d size . ? v in i o fc in ? -- -- -- -- -- -- -- -- - 1 v o v in -- -- -- -- - ? ?? ?? ?? v o v in -- -- -- -- - ? ? = i cin_r m s i o v o v in -- -- -- -- - 1 v o v in --- -- -- - - ? ?? ?? ?? ? = v o v in -- -- -- -- - m = 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 m i cin_rms (m) i o ? i l v o fl ? -- -- -- -- -- - 1 v o v in -- -- -- -- - ? ?? ?? ?? ? = i lp eak i o ? i l 2 - --- -- - - + =
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 9 of 14 output cap a ci tor th e o u tput cap a citor is sel e cte d ba sed o n the dc ou tput volt a ge r a ting, ou tp ut r i pp le voltag e specifica t i on an d r i pple cu rr ent ra tin g . th e selected o u tput ca p a cito r mu st have a h i ghe r r a ted volt a ge spe c ification tha n the ma xim u m de sir e d o u tput volt a ge in clu d ing r i pp le. de -r ating n eed s to be con s id er ed for lo ng ter m re liabili ty . output rip p le volt a ge spe c ification is ano ther i m po rt an t factor for se lectin g the ou tp ut ca p a cito r . in a b u ck con v e r ter cir c u i t, ou tp ut ripp le volt ag e is d e ter m ine d by inductor value, s witc h ing fr eq ue n cy , ou tp ut ca p a cito r valu e and esr. it ca n be calcula t e d by th e eq uation below: w h er e, c o is output cap a ci tor valu e, a nd esr co is the equ ivale n t seri es re si st an ce of the ou tpu t cap a c i tor . whe n a low esr cer a m i c ca p a ci to r is u sed as the ou tp ut cap a citor , th e imp eda nce o f the cap a cito r a t th e switchin g fr eq u e n cy do m i na te s. ou tp ut r i pp le is m a inly ca us ed b y cap a citor valu e an d ind u cto r rip p le cur r e n t. th e ou tp ut rip p l e v o lt a g e calc ula t io n ca n be sim p lifie d to : if the im ped an ce o f esr a t switchin g fr eq uen cy d o min a tes, th e ou tput r i pple vo lt ag e is ma inly de cided by cap a citor esr and in du ctor ripp le cur r en t. th e outpu t rip p l e v o lt a g e calc ula t io n ca n be fu r t he r sim p lif i ed t o : fo r lower outp u t r i pp le vo lt ag e acro ss th e en tir e o per ating temp er atur e r a n ge, x5 r or x7r d i ele c tric type of ce ra m i c, or o th e r lo w es r t a nt a l u m cap a c i to rs ar e r e comm end ed a s ou tp ut ca p a cito rs. in a bu ck conver ter , ou t put ca p a cito r curr en t is cont inuous. the r m s current of output c a p a cit o r is d e cided by th e pea k to p eak ind u cto r r i pple cu rr ent. it can be c a lc ula t e d by : usu a lly , the r i pple cur r e n t r a ting of the ou tput cap a citor is a smalle r issue be ca use of th e low cu rr en t str e ss. whe n the b u ck ind u ctor is se lected to be ver y sma ll a nd ind u ctor r i pp le cu rr ent is h i gh, the ou tp ut ca p a cito r co uld be o verstre sse d . loo p co mp ens a t i on th e aoz3 024 pi em ploys pea k cur r e n t m ode con t rol for ea se of u s e a n d fast tr ansie nt r e spo n se. pe ak cu rr en t mo de con t r o l elim inates th e do uble pole e f fe ct of the output l&c filter . it als o greatly simplifies the co m p e n s a t i on lo op d e sig n. with pea k cur r e n t m ode co ntro l, the bu ck po we r st ag e ca n be s i mp lifie d to b e a on e- po le a n d o n e - zer o sys te m in fre que ncy d o ma in. the p o le is d o min a n t po le can be ca lcu l at ed b y: th e ze ro is a esr zer o du e to the outpu t cap a citor a nd it s esr. it is can be ca lcu l ated b y : whe r e; c o is th e output fi lte r cap a citor , r l i s lo ad resistor va lue , and esr co is the equ ivale n t se ri es re sist a n ce of o u tp ut cap a citor . t h e c o m p en sa tio n de sig n sh ap es th e co nv er te r c o n t r o l loo p tran sfe r function for th e desir ed ga in an d ph ase. sever a l dif f ere n t type s of com pen sa tion ne twor ks ca n be used w i th the AOZ3024PI. for mos t c a ses, a series cap a citor a nd r e sistor networ k con nected to the comp pin se t s the pol e-ze ro an d is a deq ua te for a st a b le hig h - ban dwid th co ntro l lo op. in the aoz 302 4pi, fb an d com p ar e the inve rting inp u t an d the ou tp ut of the inter nal er ro r am plifier . a se rie s r a n d c co mpe n sation n e twor k conn ected to comp pr ovide s o ne po le an d one ze ro . th e pole is: whe r e; g ea is the erro r ampli f i e r transcon duct ance , which is 200 x 1 0 -6 a/v , g ve a is th e e rror a m p lifier volt age g a in , whi c h i s 50 0 v/v , and c c i s the compen sation cap a cito r i n f i g u re 1. ? v o ? i l esr co 1 8 fc o ? ? ---------- -- -- -- -- -- -- --- + ?? ?? ? = ? v o ? i l 1 8 fc o ? ? -- -- -- -- -- -- -- -- -- -- -- -- - ? = ? v o ? i l esr co ? = i co_rms ? i l 12 -- -- -- -- - - = f p 1 1 2 ? c o r l ? ? ---------- -- -- -- -- -- -- -- -- -- -- -- -- - = f z 1 1 2 ? c o esr co ? ? ---- - --- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - - = f p 2 g ea 2 ? c c g vea ? ? ---- - - - -- -- -- -- --- -- -- -- -- -- -- -- -- -- -- -- -- - =
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 10 of 14 th e zero g i ven by the exter nal comp en sa tio n ne twor k, cap a citor c c and resist or r c , is lo ca te d at : t o de sig n the comp ensa t io n cir cuit, a t a rg et cr osso ve r fre que ncy f c to close the lo op mu st be sele cte d . t he system cr osso ve r fre que ncy is wh er e th e contr o l loop ha s un ity ga in . t h e cro ss o ve r is t h e a l so ca lle d th e con v e r ter ban dwid th . ge ner ally a hig her ban dwid th me an s faste r r e spon se to lo ad transient s . h o wever , the b and wid t h shou ld no t be too high b e cau s e o f system st ability c o ncern. w h en de signing the compens a tion loop, c o nverter st ability under all line an d load c o ndition mu st be con s id er ed . usually , it is re co mmen d e d to se t the ba nd wid t h to be e qua l o r less th an 1/10 of the switch ing fre que ncy . the st rategy for choosing r c an d c c is to s e t the cross o v e r freq ue ncy with r c an d se t the com pen sa to r zer o with c c . u sing selected c r ossover fr equ en cy , f c , t o ca lcu l at e r c : w h er e; f c is the d e sired crossover freque ncy . fo r b e st pe rforman ce, f c is se t to b e abo ut 1/10 o f th e switching frequ ency; v fb is 0. 8v , g ea is th e e rror a m p lifier tra n scond uct a nce, w h ich is 200 x 10 -6 a/v , and g cs is the curren t sense circui t tra n scond uct a nce, w h ich is 8 a/v the c o mpensation cap a citor c c an d r e sistor r c to ge th er ma ke a ze ro . th is zer o is pu t som e wher e close to th e do m i na te p o l e f p1 but lower th an 1/5 of the sele cted cro s so ve r freq ue ncy . c c can is selected by : th e ab ove equ ation ca n be simplified to : an e a sy -t o- us e a p p lic atio n so f t wa r e w h ic h he lp s to d e sign an d sim u late the comp ensatio n lo op can be fou n d at www . ao sm d.co m . thermal management and layout considerations in th e aoz3 02 4pi b u ck r egu lator cir c u i t, hig h pu lsin g cur r e n t flows th ro ugh two circuit loop s. th e first lo op st art s from t h e input cap a cito rs, to th e vi n pin, to th e lx p ad, to th e filte r ind u ct or , t o t h e o u t pu t ca p a cito r an d load, and then returns to the in put ca p a cito r thro ug h gr ou nd. cur r ent flows in th e first loo p whe n the hig h side sw itch is on . t h e se co nd lo op s t ar t s f r o m th e ind u c t o r , to th e ou tp ut ca p a cito rs a n d lo ad, to th e low sid e nmosfe t . current fl ows in th e se co nd lo op w h e n th e low side nmosfe t is on. in pc b layout, minimizing the area of the two loop s will r edu ce th e noise o f the circuit an d impr oves ef ficie n cy . a gr oun d pla ne is stro ngly re co mme nde d to co nn ect the inp u t ca p a cito r , th e ou tp ut ca p a c i to r , an d th e pgn d p i n of th e aoz3 02 4pi. in th e aoz30 24pi b u ck r egu la tor circuit, the major power dissip a ting comp on ent s ar e th e aoz3 02 4pi a nd the ou tp ut indu cto r . the tot a l p o wer dissip a t io n of co nver te r circuit ca n be m easur ed b y in put po we r min u s o u tput po wer: th e powe r dissip a tio n of th e ind u cto r can be ap pr oximate l y calcula t e d by th e outpu t cur r e n t a n d dcr valu e of the indu ctor : t h e act u a l jun ctio n t e m p er at ur e ca n b e ca lcu l at ed b y th e po wer d i ssip ation in the aoz30 24pi an d th e th er mal imp eda nce fro m junction to am bien t: th e maximum ju nctio n te mpe r a t u r e of th e aoz3 024 pi is 150 oc, which limit s the maximu m load current cap ability . plea se se e th e th er mal de -r ating cu rves fo r maximu m loa d cur r en t o f the aoz 302 4pi u n d e r di f f er en t am bien t temp er atur es. th e th er mal pe rfor ma nce of th e aoz30 2 4 p i is stro ngly af fected by the pcb la yo ut. car e sho u ld be t a ken d u rin g the design process to ensure that the ic will operate un de r th e re comme nd ed en vir o n m en t a l cond itio ns. f z 2 1 2 ? c c r c ? ? -- -- -- -- -- -- -- -- -- -- - -- -- -- -- -- -- - - = r c f c v o v fb ---------- 2 ? c c ? g ea g cs ? -- -- -- -- -- -- -- -- -- -- -- -- -- -- - - ? ? = c c 1.5 2 ? r c f p 1 ? ? ---- -- -- -- -- -- -- -- -- -- -- -- -- --- -- - - = c c c o r l ? r c ------ - - - -- -- -- -- ---- = p total_loss v in i in v o i o ? ? ? = p inductor_lo s s i o 2 r inducto r 1. 1 ? ? = t juncti on p total_ l o s s p inducto r_ l o s s ? ?? ? ? ja =
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 11 of 14 la you t conside r at io ns th e aoz3 024 pi is an expo sed p ad so- 8 p a ckage . se ve ra l lay o u t tip s ar e liste d fo r th e be st ele ctr ic an d th er m a l pe rf or ma n ce . 1 . th e expo se d p ad (l x) is con n e c ted to the in te rn al pfet an d nfet dr ains. con n e c ted a larg e copp er pla n e to th e lx pin t o he lp th er ma l d i ss ip at ion . 2 . do no t use a th er mal re lief con n e c tion to the vin pin o r the pgnd p i n. po ur a m a ximized cop per area to the pgnd pin a nd the vin p i n to h e lp the rma l dis sip ation. 3 . th e inpu t cap a citor sho u ld be con nected as clo se a s p o ssib le to th e vin pin a nd the pgnd pin. 4 . a gr oun d pla ne is p r e f e r r e d . if a g r ou nd p l ane is no t us ed , se p a r a te pg nd f r o m agnd and o n ly co nne ct the m at o ne po int to a v o i d the pgnd pin no ise co up lin g to th e agn d p i n. 5 . ma ke th e cu rr en t tra c e fr om the lx p ad to l to co to the pgnd as sh ort as possible . 6 . pou r copp er p l an e on a ll u nused boa rd a r e a and connect it to s t able dc nodes, like vin, gnd or vout . 7 . kee p sensitive sig nal tra c e a w ay fr om the lx p ad.
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 12 of 14 package dimen s ion s , so-8 ep1 notes: 1. package body sizes exclude mold flash and gate burrs. 2. dimension l is measured in gauge plane. 3. tolerance 0.10mm unless otherwise specified. 4. controlling dimension is millimeter, converted inch dimensions are not necessarily exact. 5. die pad exposure size is according to lead frame design. 6. followed from jedec ms-012 symbols a a1 a2 b c d d0 d1 e e e1 e2 e3 l y | l1?l1' | l1 dimensions in millimeters recommended land pattern min. 1.40 0.00 1.40 0.31 0.17 4.80 3.20 3.10 5.80 ? 3.80 2.21 0.40 ? 0 ? d0 unit: mm nom. 1.55 0.05 1.50 0.406 ? 4.96 3.40 3.30 6.00 1.27 3.90 2.41 0.40 ref 0.95 ? 3 0.04 1.04 ref max. 1.70 0.10 1.60 0.51 0.25 5.00 3.60 3.50 6.20 ? 4.00 2.61 1.27 0.10 8 0.12 dimensions in inches d1 e1 e e3 e2 note 5 l1' l1 l gauge plane 0.2500 c d 7 (4x) b 3.70 2.20 2.87 2.71 5.74 1.27 0.80 0.635 e a1 a2 a symbols a a1 a2 b c d d0 d1 e e e1 e2 e3 l y | l1?l1' | l1 min. 0.055 0.000 0.055 0.012 0.007 0.189 0.126 0.122 0.228 ? 0.150 0.087 0.016 ? 0 ? nom. 0.061 0.002 0.059 0.016 ? 0.195 0.134 0.130 0.236 0.050 0.153 0.095 0.016 ref 0.037 ? 3 0.002 0.041 ref max. 0.067 0.004 0.063 0.020 0.010 0.197 0.142 0.138 0.244 ? 0.157 0.103 0.050 0.004 8 0.005
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 13 of 14 t a pe and reel dimensions, so-8 ep1 carrier tape reel tape size 12mm reel size ?330 m ?330.00 0.50 package so-8 (12mm) a0 6.40 0.10 b0 5.20 0.10 k0 2.10 0.10 d0 1.60 0.10 d1 1.50 0.10 e 12.00 0.10 e1 1.75 0.10 e2 5.50 0.10 p0 8.00 0.10 p1 4.00 0.10 p2 2.00 0.10 t 0.25 0.10 n ?97.00 0.10 k0 unit: mm b0 g m w1 s k h n w v r trailer tape 300mm min. or 75 empty pockets components tape orientation in pocket leader tape 500mm min. or 125 empty pockets a0 p1 p2 feeding direction p0 e2 e1 e d0 t d1 w 13.00 0.30 w1 17.40 1.00 h ?13.00 +0.50/-0.20 k 10.60 s 2.00 0.50 g ? r ? v ? leader/trailer and orientation unit: mm
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 14 of 14 part marking z3024pi fay part number code assembly lot code year & week code wl t fab & assembly location as us ed h e r e in : 1. life supp or t de vice s or systems are devices o r systems wh ich , (a ) ar e in tend ed for surg ical im plan t into the b ody or ( b ) su ppo rt or sust ain l i fe , an d (c) who s e failu re to pe rfor m wh en p r o per ly u s e d in accor dan ce wit h in st ru ctio ns fo r us e p r ovid e d in t h e la be lin g, ca n be r eason ab ly expe cte d to r e sult in a signi fican t inju ry of th e us er . 2. a critical comp one nt in any co mpo n e n t o f a life su pp or t, d e vice , or system whose failur e to p e rfor m ca n be r easo nab ly e x p e cte d to ca use the failur e of the life su pp or t de vice o r system, or to af fect it s sa fe ty or ef fectiven ess. legal disclaimer alpha a n d omeg a semicon d u c tor makes no r epr esen t a tion s or wa rr an tie s with resp ect to th e accur a cy or c o mpletenes s of the information prov id ed herein and t a kes no liabilities fo r the consequences of us e of such infor m ation o r an y p r o duct d e scribe d he re in. a lp ha a nd om ega se micond uctor r e ser v e s the r i gh t to make cha nge s t o such information at any time w i thout furt h e r no tice . t h is do cume nt do es no t co nstitu te the gr ant o f any i n tellectua l pr ope rty r i gh t s or re pr esent a t io n of non -in f r i ng eme n t of a n y th ird p a r t y? s intellectua l p r o per ty r i ght s. life support policy alpha & omega semiconduct or produc ts are not author ized for use as critical components in life suppor t dev i ces or systems.

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